As as is well understood, cache memory arrays are utilized as high speed buffers between a central processing unit and main storage. The CPU searches the identifier fields of all the members comprising a given addressed set of the array for a "match". If a match is found, the search for the required information is completed and the data associated with the member yielding the match is utilized by the CPU. In those instances where no match is produced after the identifier fields of all the members of a given set have been searched, the main memory is accessed for the necessary information and it is then written into the member of the addressed set containing the oldest data. The member containing the oldest data is selected in accordance with a first in - first out (FIFO) algorithm.
FIFO algorithms previously have been implemented by logic such as, for example, a binary or ring counter, external to the cache array. The external logic is repeated for each set of members within the array. Not only does the physical bulk of the required external logic circuits increase directly with increases in the number of sets comprising the cache array, but the costs of hardware, packaging and testing the combination of the array and the logic circuits increases significantly to create a very undesirable situation especially where large scale integration circuit techniques are employed.